Freescale Semiconductor MC68881 - Page 138

4
FMUL FMUL
Operation: Source x FPn I) FPn
Assembler FMUL.<fmt> <ea>,FPn
Syntax: FM U L.X FPm,FPn
Attributes: Format= (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and mul-
tiplies that number by the number in the destination floating-point data register, Stores
the result in the destination floating-point data register.
Operation Table:
So"reel
Destination ~
+
In Range
+
Zero
+
Infinity
In Range
+
Zero
+0.0 -O.O
-O.O +0.0
In~ni'W
+
+inf -inf
-inf = inf
Multiply
+0.0 -0.O +0.0 -0.0 NAN1
-0.0 +0.0 -O.0 +0.0
+ inf -inf NAN1 + inf -inf
-inf +inf -inf =inf
NOTES:
1. Sets the OPERR bit in the FPSR exception byte.
2. If the source operand is a NAN, refer to 4.5.4 NANs for more information.
Status Register:
Condition Codes:
Quotient Byte:
Exception Byte:
Accrued Exception Byte:
Affected as described in 4.5.5.1 SETTING FLOATING-POINT
CONDITION CODES
Not affected
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 4.5.4 NANs.
Set for 0 x infinity; cleared otherwise
Refer to 6.1.4 Overflow,
Refer to 6.1.5 Underflow.
Cleared
Refer to 6.1.7 Inexact Result.
If <fret> is Packed, refer to 6.1.8 Inexact Result
on
Decimal Input; cleared otherwise.
Affected as described in 6.1.10 IEEE Exception and Trap Com-
patibility
Instruction Format:
15 14 13 12
1 1 1 1
0 R/M 0
11 l0 9 8 7 5
COPROCESSOR I '
ID 0 0 0
SOURCE DESTINATION
SPECIFIER REGISTER 0
5 4 3 2 1 C
EFFECTIV~ ADDRESS
MOOE ! ~E~,~STER
FREESCALE
4-80
MC68881/MC68882 USER'S MANUAL