Freescale Semiconductor MC68881 - Page 139

FMUL FMUL
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M=0, this field is unused, and should be all zeros.
If R/M=1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode
Dn* 000
An
(An) 010
(An) + 011
- (An) 100
(d16,An) 101
(d8,An,Xn) 110
(bd,An,Xn) 110
{[bd,An,Xn},od) 110 I
([bd,An],Xn,od) 110
*Only if <fmt> is Byte, Word, Long,
Register
reg. number:Dn
reg. number:An
reg. number:An
reg. number:An
reg. number:An
,i
reg. number:An
reg. number:An
reg. number:An
reg. number:An
or Single.
Addressing Mode Mode
(xxx).W 111
(xxx).L 111
#<data > 111
(d 16,PC) 111
(d8,PC,Xn) 111
(bd,PC,Xn) 111
({bd,PC,XnJ,od) 111
([bd,PC],Xn,od) 111
Register
000
001
100
010
011
011
011
011
R/M Field m Specifies the source operand address mode.
0 -- The operation is register to register.
1 m The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M =0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field -- Specifies the destination floating-point
data register, FPn.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-81