FREM
'EEE Remainder
FREM
OVFL Cleared
UNFL Refer to 6.1.5 Underflow.
DZ Cleared
INEX2 Cleared
INEXl If <fmt> is Packed, refer to 6.1.8
Inexact Result
on Decimal
Input; cleared otherwise.
Accrued Exception Byte: Affected as described in 6.1.10
IEEE Exception and Trap Com-
patibility
Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 l 1 0
COPROCESSOR EFFECTIV[ ADDRESS
1 1 1 1 ID O 0 0 MODE REGISTER
SOURCE DESTINATION
0 R/M 0 SPECIFIER REGISTER 0 1 0 0 1 0 l
Instruction Fields:
Coprocessor ID Field --Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M--O, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register Addressing Mode Mode Register
Dn* 000 reg. number:Dn (xxx).W 111 000
An -- -- (xxx).L 111 001
{An) 010 reg. number:An #<data> 111 100
(An)+ 011 reg. number:An
- (An) 100 reg. number:An
(dlG,An) 101 reg. number:An (d16,PC) 111 010
(d8,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011
(bd,An,Xn) 110 reg. number:An (bd,PC,Xn) 111 011
([bd,An,Xnl,od) 110
reg.
number:An ([bd,PC,XnJ,od) 111 011
([bd,An],Xn,od) 110 reg. number:An
([bd,PC],Xn,od)
111 011
*Only if <fmt> is Byte, Word, Long, or Single.
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M =0, specifies the source floating-point
data
register, FPm.
If R/M = 1, specifies the source data format:
• 000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field -- Specifies the destination floating-point data register, FPn.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-87
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