FScc
Set According to Condition
FScc
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to
execute
this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field. Specifies the addressing mode for the byte integer operand:
Addressing Mode Mode Register
Dn 000 reg. number:Dn
An -- --
(An) 010
reg, number:An
(An)+ 011
reg. number:An
-(An) 100
reg. number:An
(d16,An) 101
reg. number:An
(dd,An,Xn) 110
reg. number:An
(bd,An,Xn) 110
reg. number:An
([bd,An,XnJ,od) 110
reg. number:An
([bd,An],Xn,od) 110
reg. number:An
Addressing Mode Mode Register
(xxx}.W 111 000
(xxx).L 111 001
#<data> --
--
(d16,PCl -- _
(d8,PC,Xn) -- _
(bd,PC,Xn) --
--
([bd,PC,XnJ,od)
-- --
([bd,PC],Xn,od}
--
--
Conditional Predicate Field -- Specifies one of 32 conditional tests as defined in 4.4
CONDITIONAL TEST DEFINITIONS.
NOTE
When a BSUN exception occurs, a pre-instruction exception is taken by the
main processor. If the exception handier returns without modifying the image
of the PC on the stack frame (to point to the instruction following the FScc),
then it must clear the cause of the exception (by clearing the NAN bit or
disabling the BSUN trap) or the exception occurs again immediately upon
return to the routine that caused the exception.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-97
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