4
FSGLDIV Single Precision Divide FSGLDIV
Operation:
FPn (-) Source 0 FPn
Assembler
FSGLDIV.<fmt> <ea>,FPn
Syntax:
FSGLDIV.X FPm,FPn
Attributes:
Format= (Byte, Word, Long, Single, Double, Extended, Packed)
Description:
Converts the source operand to extended precision (if necessary) and di-
vides that number into the number in the destination floating-point data register.
Stores the result in the destination floating-point data register, rounded to single
precision (regardless of the current rounding precision). This function is undefined for
0( ÷ )0 and infinity( + )infinity.
Both the source and destination operands are assumed to be representable in the
single precision format. If either operand requires more than 24 bits of mantissa to
be accurately represented, the accuracy of the result is not guaranteed. Furthermore,
the result exponent may exceed the range of single precision, regardless of the round-
ing precision selected in the FPCR mode control byte. Refer to 4.5.5.2 UNDERFLOW,
ROUND, OVERFLOW for more information.
Operation Table:
Source
Destination
~
+
In Range
+
Zero
+
Infinity
In Range ]
+
Divide
(Single Precision)
Zero
+
inf 1 -infl
-inf ~ +iof 1
I Infinity
+
+0.0 -0.0
- 0.0 - 0.0
+0.0 -0.0 NAN2 +0.0 -0.0
-0.0 +0.0 -0.0 -0.0
+inf -inf ÷inf -inf NAN2
inf +inf -inf +inf
NOTES:
1. Sets the DZ bit in the FPSR exception byte.
2. Sets the OPERR bit in the FPSR exception byte.
3. If the source operand is a NAN, refer to 4.5.4 NANs for more information.
Status Register:
Condition Codes:
Quotient Byte:
Exception Byte:
Affected as described in 4.5.5.1 SETTING FLOATING-POINT
CONDITION CODES
Not affected
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 4.5.4
NANs.
Set for 0(+ )0 or infinity( + )infinity
Refer to 6.1.4 Overflow.
Refer to 6.1.5 Underflow.
Set if the source is zero and the destination is
in range; cleared otherwise
Refer to 6.1.7
Inexact Result.
If <fret> is Packed, refer to 6.1.8 Inexact
Result
on Decimal
Input; cleared otherwise.
FREESCALE
4-98
MC68881/MC68882 USER'S MANUAL
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