Freescale Semiconductor MC68881 - Page 157

FSGLDIV Single Precision Divide FSGLDIV
Accrued Exception Byte: Affected as described in 6.1.10 IEEE Exception and Trap
Compatibility
Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O
I COPROCESSOR EFFECTIV~
ADDRESS
1 1 1 1 iD 0 0 0 MODE | REGISTER
I
/
SOURCE DESTINATION
I 0 o ~ 0
0 R/M 0 SPECIFIER REGISTER 0 1 0
I
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID-- 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register
Dn* DO0 reg, number:Dn
An -- --
(An) 010
reg. number:An
(An)+ 011 reg. number:An
--(An) t00 reg. number:An
Id16,An) 101 reg. number:An
(ds,An,Xn) 110 reg. number:An
(bd,An,Xn) 110 reg. number:An
([bd,An,Xnl,od) 110 reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Only if <fret> is Byte, Word, Long, or Single.
Addressing Mode Mode
(xxx).W 11 i
(xxx),L 111
#<data> 111
(d16,PC) 111
(d8,PC,Xn) 111
(bd,PC,Xn) 111
([bd,PC,Xnl,od) 111
([bd,PCJ,Xn,od) 111
Register
000
001
100
010
011
011
011
011
R/M Field --Specifies the Source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field -- Specifies the destination floating-point data register, FPn.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-99