4
FSGLMUL Single Precision Multiply FSGLMU L
Operation:
Source ×
FPn ~ FPn
Assembler
FSGLMUL.<fmt>
Syntax:
FSGLMUL.X
<ea>,FPn
FPm,FPn
Attributes: Format= (Byte, Word, Long, Single, Double, Extended, Packed)
Description:
Converts the source operand to extended precision (if necessary) and mul-
tiplies that number by the number in the destination floating-point data register. Stores
the result in the destination floating-point data register, rounded to single precision
(regardless of the current rounding precision).
Both the source and destination operands are assumed to be representable in the
single precision format. If either operand requires more than 24 bits of mantissa to
be accurately represented, the accuracy of the result is not guaranteed. Furthermore,
the result exponent may exceed the range of single precision, regardless of the round-
ing precision selected in the FPCR mode control byte. Refer to 4.5.5.2 UNDERFLOW,
ROUND, OVERFLOW for more information.
Operation Table:
Source
Destination
.~_
+
In Range
In
Range
+
Multiply
(Single Precision
Zero
+
+0.0 -0.0
-0.0 ~0.0
Infinity
+
+inf -inf
-inf + inf
Zero + ÷O.0 -0.0 +0.O -0.O NAN1
- -0.O +0.0 -0.0 +0.0
Infinity + + inf - inf +inf - inf
- -inf +inf NAN1 -inf +inf
NOTES:
1. Sets the OPERR bit in the FPSR exception byte.
2. If the source operand is a NAN, refer to 4.5.#,
NANs
for more
information.
Status Register:
Condition Codes:
Affected as described in 4.5.5.1 SETTING FLOATING-POINT
CONDITION CODES
Quotient Byte: Not affected
Exception Byte: BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
Cleared
Refer to 4.5.4
NANs.
Set if one operand is
zero
and the other is in-
finity; cleared otherwise
Refer to 6.1.4 Overflow.
Refer to 6.1.5 Underflow.
Cleared
Refer to 6.1.7 Inexact
Result.
FREESCALE
4-100
MC68881/MC68882 USER'S MANUAL
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