Freescale Semiconductor MC68881 - Page 159

FSGLMUL Sing,e Precision Multiply FSGLMUL
INEX1 If <fmt> is Packed, refer to 6.1.8 Inexact Result
on Decimal Input; cleared otherwise.
Accrued ExceptiOn Byte: Affected as described in 6.1.10 IEEE Exception and Trap
Compatibility
Instruction Format:
,5 ~, ,3 ,, ,0 , 8 , 5 , 3 2 1 0
coPRocEss0, ~- - ---
1 LJ_E~EEC~ VE ~OORES~, 1
,ou,,, o,..,...,o. %'0"
0 R/M 0 SPECIFIER REGISTER ] 1
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freesoale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register
Dn* 0O0 reg. number:Dn
An -- --
(An) 010
reg. number:An
(An)+ 011 reg. number:An
-(An) 100 reg. number:An
(d16,An) 101 reg. number:An
(ds,An,Xn) 110 reg, number:An
(bd,An,Xn) 110 reg. number;An
(Ibd,An,Xn],od) 110 reg, number:An
([bd,AnJ,Xn,od) 110 reg. number:An
*Only if <fret> is Byte, Word, Long, or Single.
Addressing Mode Mode
(xxx).W 111
(xxx).L 111
#<data> 111
(d16,PC) 111
(d8,PC,Xn) 111
(bd,PC,Xn) 111
([bd,PC,XnJ,od) 111
([bd,PC],Xn,od) 111
Register
O00
001
100
010
011
011
011
011
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M =0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field-- Specifies the destination floating-point
data register, FPn.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-101