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Freescale Semiconductor MC68881 - Page 169

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FSUB
Subtract
FSUB
Operation:
FPn - Source I) FPn
Assembler
FSUB.<fm~;> <ea>,FPn
Syntax:
FSUB.X FPm,FPn
Attributes:
Format= (Byte, Word, Long, Single, Double, Extended, Packed)
Description:
Converts the source operand to extended precision (if necessary) and sub-
tracts that number from the number in the destination floating-point data register.
Stores the result in the destination floating-point data register.
Operation Table:
•
Source
Destination
In Range +
In
Range
+
Subtract
Zero
+
Subtract
Infinity
+
- inf + inf
Zero + Subtract + 0'01 - 0.0 - inf + inf
- -0.0 +0.01
Infinity + + inf + inf NAN 2 -inf
- -inf -inf -inf NAN 2
NOTES:
1. Returns +0,0 in rounding modes RN, RZ, and RP; returns -0.0 in RM,
2. Sets the OPERR bit in the FPSR exception byte.
3. If the source operand is a NAN, refer to 4.5.4 NANs for more information.
Status Register:
Condition Codes:
Affected as described in 4.5.5.1 SETTING FLOATING-POINT
CONDITION CODES
Quotient Byte: Not affected
Exception Byte: BSUN
SNAN
OPERR
Cleared
Refer to 4.5.4
NANs.
Set if both the source and destination are like-
signed infinities; cleared otherwise
OVFL Refer to 6.1.4 Overflow.
UNFL Refer to 6.1.5 Underflow.
DZ Cleared
INEX2 Refer to 6.1.7 Inexact
Result.
INEXl If <fmt> is Packed, refer to 6.1.8
Inexact Result
on
Decimal Input; cleared otherwise.
Affected as described in 6.1.10 IEEE Exception
and Trap
Compatibility
Accrued Exception Byte:
MC68881/MC68882 USER'S MANUAL
FREESCALE
4-111

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