Freescale Semiconductor MC68881 - Page 170

4
FSUB Subtract FSUB
Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COPROCESSOR 1 I EFFECTIVE ADDRESS
l , , , ,D 0 0 0 MODE REGISTER
SOURCE DESTINATION i
O RIM 0 SPECIFIER REGISTER 0101000
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID= 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
.Addressing Mode " Mode Register
Dn* 000 reg. number:Dn
An -- --
(An) 010
reg. number:An
(An)+ 011 reg. number:An
-(An) 100 reg. number:An
(d16,An) 101 reg. number:An
(dG,An,Xn) 110 reg. number:An
(bd,An,Xn) 110 reg. number:An
([bd,An,Xn],od) 110 reg. number:An
([bd,AnJ,Xn,od) 110 reg. number:An
*Only if <fmt> is Byte, Word, Long, or Single.
Addressing Mode
(xxx).W
Mode I Register
(d8,PC,Xn)
111
(xxx).L i 111 031
#<data> 111 I 103
I
I
{d16,PC) 111 I 010
011
Ibd,PC,Xn)
([bd,PC,Xn],ocl)
([bd,PC},Xn,od)
111 J
00:3
011
I
111 I 011
111 t 011
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M = O, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field -- Specifies the destination floating-point data register, FPn.
FREESCALE
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MC68881/MC68882 USER'S MANUAL