4
FTST
Test Operand
FTST
Instruction Fields:
Coprocessor ID Field ~ Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID= 1 for the FPCP.
Effective Address Field ~ Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register
Dn* 0go reg. number:Dn
An -- --
(An) 010 reg. number:An
(An)+ 011 reg. number:An
-(An) 100 reg. number:An
(d 16,An) 101 reg. number:An
(d8,An,Xn) 110 reg. number:An
(bd,An,Xn) 110 reg. number:An
([bd,An,Xn],od) 110 reg. number:An
([bd,AnJ,Xn,od)
110 reg. number:An
*Only if <fmt> is Byte, Word,
Long, or Single.
Addressing Mode
(xxx).W
(xxx).L
#<data>
Mode
Register
111 000
111 001
111 t 100
(d16,PC} 111 010
(ds, PC,Xn) 111 011
(bd,PC,Xn) 111 011
([bd,PC,Xn],od) 111 011
([bd,PC],Xn,od) 111 011
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M =0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field -- Since the FPCP uses a common command word format
for all of the arithmetic instructions (including FTST), this field is treated in the same
manner for FTST as for the other arithmetic instructions, even though the destination
register is not modified. This field should be set to zero in order to maintain com-
patibility with future devices, although the FPCP does not signal an illegal instruction
trap if it is not zero.
FREESCALE
4-122
MC68881/MC68882 USER'S MANUAL
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