Freescale Semiconductor MC68881 - Page 79

FACOS Arc Cosine FACOS
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID= 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register
Dn* 000 reg. number:Dn
An -- --
(An) 010 reg. number;An
(An) ÷ 011 reg. number:An
- (An) 100 reg. number:An
(d 16,An) 101 reg. number:An
(d8,An,Xn} 110 reg. number:An
(bd,An,Xn) 110 reg. number:An
((bd,An,XnJ,od) 110 reg. number:An
([bd,AnI,Xn,od) 110 reg. number:An
*Only if <fmt> is Byte, Word, Long, or Single.
Addressing Mode Mode Register
(xxx).W 111 000
(xxx).L 111 001
#<data". 111 100
(d16,PC) 111 010
(ds,PC,Xn) 111 011
(bd,PC,Xn) 111 011
([bd,PC,Xn),od) 111 011
([bd,PC],Xn,od) 111 011
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 --The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field -- Specifies the destination floating-point data register, FPn.
If R/M=0 and the source and destination fields are equal, then the input operand
is taken from the specified floating-point data register, and the result is then written
into the same register. If the single register syntax is used, Freescale assemblers
set the source and destination fields to the same value.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-21