MAX32660 User Guide
Maxim Integrated Page 137 of 195
The I
2
C controller can hold SCL low in both master and slave modes after an ACK bit transmission.
2
C Bus Specification only applies if performed by a slave device. When an I
2
C master holds the
SCL line low, the master is technically varying the clock speed. The master can vary the clock speed from DC (0Hz) up to the
maximum
. For simplicity, this section describes situations where either an external slave or external master holds the
SCL line low.
For clock stretching, SCL is held low after an ACK bit and before the first data bit. This is often done when a receiver cannot
receive more data (usually from a full RX FIFO), or a transmitter needs to send more data but is not ready (usually from an
empty TX FIFO).
However, during Interactive Receive Mode (IRXM), the receiver begins clock stretching before the ACK bit, allowing
firmware time to decide whether to send an ACK or NACK. If operating in IRXM (I2Cn_CTRL0.irxm=1) as a slave with clock
stretching disabled (I2Cn_CTRL0.sclstrd=1), SCL is not held low. Thus, the burden is on firmware to respond quickly enough
to meet the data setup timing requirements as a late ACK could cause a transition on SDA while SCL is high, resulting in an
unwanted STOP or RESTART. For these reasons, it is not recommended to use interactive receive mode with slave clock
stretching disabled.
For a transmit operation as either master or slave, when the TX FIFO is empty after the last byte is shifted out, SCL is
automatically held low until data is written to the TX FIFO. Master transmitters can stop clock stretching in this situation to
end the transaction by sending a START or RESTART condition. When a slave transmitter sees an external master end the
transaction by sending a NACK, it can then release SDA.
12.5 I
2
C Bus Timeout
The Timeout register, I2Cn_TIMEOUT.to, is used to detect bus errors. Equation 12-1 and Equation 12-2 show equations for
calculating the maximum and minimum timeout values based on the value loaded into the I2Cn_TIMEOUT.to field.
Equation 12-1: I
2
C Timeout Maximum
Due to clock synchronization, the timeout is guaranteed to meet the following minimum time calculation shown in Equation
12-2.
Equation 12-2: I
2
C Timeout Minimum
The timeout feature is disabled when I2Cn_TIMEOUT.to = 0 and is enabled for any non-zero value. When the timeout is
enabled, the timeout timer starts counting when the I
2
C peripheral hardware drives SCL low and is reset by the I
2
C
peripheral hardware when the SCL line is released.
The timeout counter only monitors if the I
2
C peripheral hardware is driving the SCL line low. It does not monitor if an
external I
2
C device is actively holding the SCL line low. The I
2
C peripheral does not monitor the status of the SDA line.
If the timeout timer expires, a bus error condition has occurred. When a timeout error occurs, the I
2
C peripheral hardware
release the SCL and SDA lines and sets the timeout error interrupt flag to 1 (I2Cn_INTFL0.toeri = 1).
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