Maxim Integrated MAX32660 - Page 60

MAX32660 User Guide
Maxim Integrated Page 60 of 195
Following a POR event GPIO[2:13] are configured with the following default settings:
• GPIO mode enabled
 GPIO0_AF0_SEL[pin] = 1
 GPIO0_AF1_SEL[pin] = 0
• Pull-up/Pull-down disabled, I/O in Hi-Z mode
 GPIO0_PULL_EN[pin] = 0
• Output mode disabled
 GPIO0_OUT_EN[pin] = 0
• Interrupt disabled
 GPIO0_INT_EN[pin] = 0
Note: On parts without a SWD JTAG port, the SWD JTAG port is still available for boundary scan testing, however, the SWD
JTAG port is hardware disabled. To use the SWD JTAG pins in I/O mode, set the desired GPIO pins for SWD alternate function
and set the JTAG SWD disable field to 1 (GCR_SCON.swd_dis = 1).
6.2.1 I/O Mode and Alternate Function Selection
Each I/O pin supports standard GPIO mode or one of up to three Alternate Function modes. The alternate functions
assigned to each I/O pin are shown in the pin description table for the specific package. See Table 6-1 for the 16-WLP, and
Table 6-2 for the 20-TQFN.
6.2.2 Input mode configuration
Perform the following steps to configure a pin or pins for input mode:
1. Set the pin for I/O mode
a. GPIO0_AF0_SEL[pin] = 1
b. GPIO0_AF1_SEL[pin] = 0
2. Configure the pin for pull-up, pull-down, or high-impedance mode. Refer to GPIO_PULL_SEL register for pull-up
and pull-down selection
3. GPIO pins with I
2
C as an alternate function (GPIO[9:8] and GPIO[3:2]) only support high-impedance mode or a
weak pull-down resistor.
4. Set GPIO0_PULL_EN[pin] to 1 to enable the pull resistor or clear the bit to set the input to high impedance mode.
5. Read the input state of the pin using the GPIO0_IN[pin] field.
6.2.3 Output Mode Configuration
Perform the following steps to configure a pin for output mode:
1. Set the pin for I/O mode.
a. GPIO0_AF0_SEL[pin] = 1
b. GPIO0_AF1_SEL[pin] = 0
c. Enable the output buffer for the pin by setting GPIO0_OUT_EN[pin] to 1.
2. Set the output drive strength using the GPIO0_DS1_SEL [pin] and GPIO0_DS0_SEL[pin] bits.
a. Refer to the GPIO Drive Strength for configuration details and the modes supported.
b. Reference the MAX32660 datasheet for the electrical characteristics for the drive strength modes.
3. Set the output high or low using the GPIO0_OUT[pin] bit.
6.2.4 GPIO Drive Strength
Each I/O pin supports multiple selections for drive strength. Standard GPIO pins are configured for the supported modes
using the GPIO0_DS1_SEL and GPIO0_DS0_SEL registers as shown in Table 6-3, below.