Maxim Integrated MAX32660 - Page 9

MAX32660 User Guide
Maxim Integrated Page 9 of 195
List of Tables
Table 3-1: APB Peripheral Base Address Map ......................................................................................................... 19
Table 4-1: Operating Voltage Range Selection and the Effect on V
CORE
and f
HFIO
.................................................... 21
Table 4-2: Minimum Flash Wait State Setting for Each OVR Setting (f
SYSCLK
= f
HFIO
)................................................. 23
Table 4-3: Reset Sources and Effect on Oscillator Status ........................................................................................ 25
Table 4-4: Reset Sources and Effect on System Oscillator Selection and Prescaler ................................................ 25
Table 4-5: Wake-Up Sources for Each Low-Power Mode........................................................................................ 28
Table 4-6: Reset and Low Power Mode Effects ....................................................................................................... 29
Table 4-7: Instruction Cache Controller Register Addresses and Descriptions ....................................................... 31
Table 4-8: ICC Cache ID Register .............................................................................................................................. 31
Table 4-9: ICC Memory Size Register ....................................................................................................................... 31
Table 4-10: ICC Cache Control Register ................................................................................................................... 32
Table 4-11: ICC Invalidate Register .......................................................................................................................... 32
Table 4-12: Global Control Registers, Offsets and Descriptions.............................................................................. 33
Table 4-13: System Control Register ....................................................................................................................... 33
Table 4-14: Reset 0 Register .................................................................................................................................... 34
Table 4-15: System Clock Control Register .............................................................................................................. 36
Table 4-16: Power Management Register ............................................................................................................... 38
Table 4-17: Peripheral Clock Disable 0 Register ...................................................................................................... 38
Table 4-18: Memory Clock Control Register ........................................................................................................... 40
Table 4-19: Memory Zeroization Control Register .................................................................................................. 42
Table 4-20: System Status Flag Register .................................................................................................................. 42
Table 4-21: Reset Register 1 .................................................................................................................................... 43
Table 4-22: Peripheral Clock Disable Register 1 ...................................................................................................... 43
Table 4-23: Event Enable Register ........................................................................................................................... 44
Table 4-24: Revision Register .................................................................................................................................. 44
Table 4-25: System Status Interrupt Enable Register .............................................................................................. 44
Table 4-26: System Initialization Registers, Offsets and Descriptions .................................................................... 44
Table 4-27: Function Control Register 0 .................................................................................................................. 45
Table 4-28: System Initialization Address Error Register ........................................................................................ 45
Table 4-29: Function Control Registers, Offsets and Descriptions .......................................................................... 45
Table 4-30: Function Control Register 0 .................................................................................................................. 45
Table 4-31: Power Sequencer Low Power Control Registers, Offsets, Access and Descriptions ............................ 46
Table 4-32: Low Power Voltage Control Register .................................................................................................... 47
Table 4-33: Low Power Mode Wakeup Flags for GPIO0 ......................................................................................... 49
Table 4-34: Low Power Wakeup Enable for GPIO0 Register ................................................................................... 49
Table 4-35: RAM Shut Down Register ..................................................................................................................... 49
Table 5-1: Internal Flash Memory Organization ...................................................................................................... 51
Table 5-2: Valid Addresses for 32-bit and 128-bit Internal Flash Writes ................................................................ 52
Table 5-3: Page Boundary Address Range for Page Erase Operations .................................................................... 53
Table 5-4: Flash Controller Registers, Offsets, Access and Descriptions ................................................................. 54
Table 5-5: Flash Controller Interrupt Register ......................................................................................................... 56
Table 5-6: Flash Controller Data Register 0 ............................................................................................................. 57
Table 5-7: Flash Controller Data Register 1 ............................................................................................................. 57
Table 5-8: Flash Controller Data Register 2 ............................................................................................................. 57
Table 5-9: Flash Controller Data Register 3 ............................................................................................................. 57
Table 6-1: GPIO Port, Pin Name and Alternate Function Matrix, 16-WLP .............................................................. 59