Maxim Integrated MAX32660 - Page 10

MAX32660 User Guide
Maxim Integrated Page 10 of 195
Table 6-2: GPIO Port, Pin Name and Alternate Function Matrix, 20-TQFN ............................................................ 59
Table 6-3: Standard GPIO Drive Strength Selection ................................................................................................ 61
Table 6-4: GPIO with I
2
C Alternate Function Drive Strength Selection ................................................................... 61
Table 6-5: GPIO Mode and Alternate Function Selection ....................................................................................... 61
Table 6-6: GPIO Port Interrupt Vector Mapping ..................................................................................................... 62
Table 6-7: GPIO Wakeup Interrupt Vector .............................................................................................................. 62
Table 6-8: GPIO Port 0 Registers ............................................................................................................................. 63
Table 6-9: GPIO Alternate Function 0 Select Register ............................................................................................. 63
Table 6-10: GPIO Output Enable Register ............................................................................................................... 64
Table 6-11: GPIO Output Register ........................................................................................................................... 64
Table 6-12: GPIO Input Register .............................................................................................................................. 65
Table 6-13: GPIO Port Interrupt Mode Register ...................................................................................................... 65
Table 6-14: GPIO Port Interrupt Polarity Registers ................................................................................................. 65
Table 6-15: GPIO Port Interrupt Enable Registers ................................................................................................... 65
Table 6-16: GPIO Interrupt Flag Register ................................................................................................................. 66
Table 6-17: GPIO Wakeup Enable Registers ............................................................................................................ 66
Table 6-18: GPIO Interrupt Dual Edge Mode Registers ........................................................................................... 66
Table 6-19: GPIO Pullup/Pulldown Enable Register ................................................................................................ 67
Table 6-20: GPIO Alternate Function Select Register .............................................................................................. 67
Table 6-21: GPIO Input Hysteresis Enable Register ................................................................................................. 67
Table 6-22: GPIO Slew Rate Enable Register ........................................................................................................... 67
Table 6-23: GPIO Drive Strength 0 Select Register .................................................................................................. 68
Table 6-24: GPIO Drive Strength 1 Select Register .................................................................................................. 69
Table 6-25: GPIO Pullup/Pulldown Select Register ................................................................................................. 70
Table 7-1: DMA Channel Registers .......................................................................................................................... 71
Table 7-2: Channel Reload Registers ....................................................................................................................... 72
Table 7-3: Source and Destination Address Definition ........................................................................................... 73
Table 7-4: Data movement from source to DMA FIFO ............................................................................................ 73
Table 7-5: Data movement from the DMA FIFO to destination .............................................................................. 74
Table 7-6: Standard DMA Control Registers, Offsets, Access and Descriptions ...................................................... 77
Table 7-7: DMA Interrupt Enable Register .............................................................................................................. 77
Table 7-8: DMA Interrupt Flag Register ................................................................................................................... 77
Table 7-9: Standard DMA Channel 0 to Channel 15 Offsets ................................................................................... 78
Table 7-10: DMAn Channel Registers, Offsets, Access and Descriptions ................................................................ 78
Table 7-11: DMA Configuration Register ................................................................................................................. 79
Table 7-12: DMA Status Register ............................................................................................................................. 81
Table 7-13: DMA Source Register ............................................................................................................................ 82
Table 7-14: DMA Destination Register .................................................................................................................... 82
Table 7-15: DMA Count Register ............................................................................................................................. 82
Table 7-16: DMA Source Reload Register ................................................................................................................ 83
Table 7-17: DMA Destination Reload Register ........................................................................................................ 83
Table 7-18: DMA Count Reload Register ................................................................................................................. 83
Table 8-1: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps, f
PCLK
=48MHz ................................ 86
Table 8-2: UART Registers, Offset Addresses and Descriptions .............................................................................. 87
Table 8-3: UART Control 0 Register ......................................................................................................................... 87
Table 8-4: UART Control 1 Register ......................................................................................................................... 89
Table 8-5: UART Status Register .............................................................................................................................. 90
Table 8-6: UART Interrupt Enable Register ............................................................................................................. 91