Maxim Integrated MAX32660 - Page 11

MAX32660 User Guide
Maxim Integrated Page 11 of 195
Table 8-7: UART Interrupt Flags Register ................................................................................................................ 92
Table 8-8: UART Rate Integer Register .................................................................................................................... 93
Table 8-9: UART Baud Rate Decimal Register.......................................................................................................... 93
Table 8-10: UART FIFO Register ............................................................................................................................... 94
Table 8-11: UART DMA Configuration Register ....................................................................................................... 94
Table 8-12: UART TX FIFO Data Output Register ..................................................................................................... 94
Table 9-1. RTC Registers, Offsets and Descriptions ............................................................................................... 100
Table 9-2: RTC Seconds Counter Register ............................................................................................................. 100
Table 9-3: RTC Sub-Seconds Counter Register ...................................................................................................... 101
Table 9-4: RTC Sub-Seconds Counter Register ...................................................................................................... 101
Table 9-5: RTC Sub-Second Alarm Register ........................................................................................................... 101
Table 9-6: RTC Control Register ............................................................................................................................. 101
Table 9-7: RTC Trim Register ................................................................................................................................. 103
Table 10-1: Timer Register Offsets, Names, Access and Descriptions .................................................................. 122
Table 10-2: Timer Count Registers ........................................................................................................................ 122
Table 10-3: Timer Compare Registers ................................................................................................................... 122
Table 10-4: Timer PWM Registers ......................................................................................................................... 123
Table 10-5: Timer Interrupt Registers ................................................................................................................... 123
Table 10-6: Timer Control Registers ...................................................................................................................... 123
Table 11-1: Watchdog Timer Interrupt Period with f
SYSCLK
= 96MHz and f
PCLK
= 48MHz ........................................ 127
Table 11-2: Watchdog Timer Registers ................................................................................................................. 129
Table 11-3: Watchdog Timer Control Register ...................................................................................................... 129
Table 11-4: Watchdog Timer Reset Register ......................................................................................................... 130
Table 12-1: I
2
C Bus Terminology ............................................................................................................................ 131
Table 12-2: I
2
C Address Byte Format ..................................................................................................................... 138
Table 12-3: I
2
C Registers ........................................................................................................................................ 144
Table 12-4: I
2
C Control Registers 0 ........................................................................................................................ 145
Table 12-5: I
2
C Status Registers ............................................................................................................................. 147
Table 12-6: I
2
C Interrupt Status Flags Registers 0 ................................................................................................. 148
Table 12-7: I
2
C Interrupt Enable 0 Registers.......................................................................................................... 150
Table 12-8: I
2
C Interrupt Status Flags 1 Registers ................................................................................................. 151
Table 12-9: I
2
C Interrupt Enable Registers 1.......................................................................................................... 151
Table 12-10: I
2
C FIFO Length Registers .................................................................................................................. 152
Table 12-11: I
2
C Receive Control Registers 0 ......................................................................................................... 152
Table 12-12: I
2
C Receive Control 1 Registers ......................................................................................................... 153
Table 12-13: I
2
C Transmit Control Registers 0 ....................................................................................................... 153
Table 12-14: I
2
C Transmit Control Registers 1 ....................................................................................................... 154
Table 12-15: I
2
C Data Registers ............................................................................................................................. 155
Table 12-16: I
2
C Master Mode Control Registers .................................................................................................. 155
Table 12-17: I
2
C SCL Low Control Register ............................................................................................................ 156
Table 12-18: I
2
C SCL High Control Register ............................................................................................................ 156
Table 12-19: I
2
C Timeout Registers ....................................................................................................................... 156
Table 12-20: I
2
C Timeout Registers ....................................................................................................................... 157
Table 12-21: I
2
C Slave Address Register ................................................................................................................ 157
Table 12-22: I
2
C DMA Register .............................................................................................................................. 158
Table 13-1: Four-Wire SPI Signals .......................................................................................................................... 160
Table 13-2: Three-Wire SPI Signals ........................................................................................................................ 161
Table 13-3: SPI0 Pins.............................................................................................................................................. 162