VNA concepts and features
R&S
®
ZNL/ZNLE
288User Manual 1178.5966.02 ─ 20
Since FW version 1.93, the "capacitance C<i> in parallel with resistance R<i>" circuit
blocks can alternatively be represented as "capacitance C<i> in parallel with conduc-
tance G<i>" circuit blocks.
9.6.2.5 Port pair de-/embedding
Port pair de-/embedding extends the functionality of balanced port de-/embedding to
pairs of single-ended physical ports. The analyzer uses the 4-port transformation net-
works known from balanced port de-/embedding, however, each transformation net-
work is assigned to an arbitrary pair of (single-ended) physical ports.
A simple circuit which can be modeled using port pair (de-)embedding is a circuit (e.g.
a resistance) between two ports of a DUT. To obtain the circuit in the following figure,
select port pair 1,2 and the Serial Ls, Shunt L transformation network with all inductan-
ces set to zero (L1 = L2 = L3 = 0 H) and R1 = R2 = 0 Ω.
To model a general (de-)embedding network for ports 1 and 2, select port pair 1, 2 and
a 4-Port Touchstone file.
The R&S ZNL/ZNLE FW handles Port Pair De-/Embedding as a special case of Port
set de-/embedding.
9.6.2.6 Port set de-/embedding
The port set de-/embedding feature allows de-/embedding a linear 2m-port network
connecting m physical VNA ports to m physical DUT ports (m≥2).
Offset parameters and de-/embedding
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