Renesas M32R/ECU Series User Manual

4
4-15
EIT
32180 Group User’s Manual (Rev.1.0)
4.9 Interrupt Processing
4.9 Interrupt Processing
4.9.1 Reset Interrupt (RI)
[Occurrence Conditions]
A reset interrupt is unconditionally accepted in any machine cycle by pulling the RESET# input signal low.
The reset interrupt is assigned the highest priority among all EITs.
[EIT Processing]
(1) Initializing SM, IE and C bits
The PSW register’s SM, IE and C bits are initialized as shown below.
SM ← 0
IE ← 0
C ← 0
For the reset interrupt, the values of SM, IE and C bits are undefined.
(2) Branching to the EIT vector entry
The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode,
the CPU jumps to the boot program. For details, see Section 6.5, “Programming the Internal Flash Memory.”
(3) Jumping from the EIT vector entry to the user program
The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In
the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of
the user program.
4.9.2 System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault
condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW
register IE bit.
Therefore, the system break interrupt can only be used when the system has some fatal event already existing in
it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI
handler, control will not return to the program that was being executed when the system break interrupt occurred.
[Occurrence Conditions]
A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot
be masked by the PSW register IE bit.)
In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that
starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately
after branching.) Note also that because of the instruction processing-completed type, a system break
interrupt is accepted after the instruction is completed.

Renesas M32R/ECU Series Specifications

General

Brand	Renesas
Model	M32R/ECU Series
Category	Computer Hardware
Language	English

Summary

Before Use

Guide to Understanding the Register Table

Explains the conventions used in register tables, including bit numbering, register borders, status after reset, shaded bits, and read/write conditions.

CHAPTER 1 OVERVIEW

1.1 Outline of the 32180 Group

Provides an overview of the 32180 group, belonging to the M32R/ECU series of Mitsubishi microcomputers.

1.3 Pin Functions

Describes the functions of each pin on the 32180, including primary and alternative functions.

1.4 Pin Assignments

Provides the pin assignment diagram and table for the 240QFP package.

CHAPTER 4 EIT

4.2 EIT Events

Details the types of exceptions (RIE, AE, FPE), underflow, inexact, and zero division exceptions.

CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5.2 ICU Related Registers

Shows a register map associated with the Interrupt Controller (ICU), including Interrupt Vector Register and Interrupt Request Mask Register.

CHAPTER 6 INTERNAL MEMORY

6.1 Outline of the Internal Memory

Details the types of memory contained within the 32180: 48-Kbyte RAM and 1-Mbyte flash memory.

6.5 Programming the Internal Flash Memory

Explains the methods for programming or erasing the internal flash memory, including boot mode and single-chip mode.

CHAPTER 7 RESET

7.1 Outline of Reset

Describes the microcomputer reset mechanism via the RESET# input pin and the execution from the reset vector entry.

7.2 Reset Operation

Details reset operations such as power-on reset, reset during operation, reset at entering RAM backup mode, and reset vector relocation during flash programming.

CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.1 Outline of Input/Output Ports

Details the total number of input/output ports and their dual/triple function capabilities.

8.2 Selecting Pin Functions

Explains how pin functions are selected based on the current operation mode or by setting port operation mode registers.

8.3 Input/Output Port Related Registers

Lists the port data registers, port direction registers, and port operation mode registers.

CHAPTER 9 DMAC

9.2 DMAC Related Registers

Shows a memory map of the DMAC related registers, including channel control, source address, and destination address registers.

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers

Introduces the multijunction timers (MJT), their input/output event buses, and the six types of MJT provided.

10.2 Common Units of Multijunction Timers

Details the common units within MJTs: Prescaler, Clock Bus, Input/Output Event Bus Control, Input Processing, Output Flip-flop, and Interrupt Control Units.

10.3 TOP (Output-Related 16-Bit Timer)

Describes the TOP timer, its specifications, modes of operation (single-shot, delayed, continuous), and interrupt generation.

CHAPTER 11 A-D CONVERTERS

11.2 A-D Converter Related Registers

Shows the A-D converter related register map, including single mode, scan mode, and data registers.

11.3 Functional Description of A-D Converters

Explains how to find analog input voltages, A-D conversion by successive approximation, comparator operation, and conversion time.

CHAPTER 12 SERIAL I/O

12.2 Serial I/O Related Registers

Shows the serial I/O related register map, including interrupt and buffer registers.

CHAPTER 13 CAN MODULE

13.2 CAN Module Related Registers

Provides the CAN module related register map, covering control, status, frame format, and mask registers.

CHAPTER 14 REAL TIME DEBUGGER (RTD)

14.1 Outline of the Real-Time Debugger (RTD)

Explains the RTD as a serial I/O for reading/writing internal RAM locations via external commands without stopping the CPU.

14.3 Functional Description of the RTD

Details RTD operations for commands like VER, VEI, RDR, WRR, and RCV.

CHAPTER 15 EXTERNAL BUS INTERFACE

15.2 External Bus Interface Related Registers

Shows the register map for the external bus interface, including port operation mode registers.

CHAPTER 16 WAIT CONTROLLER

16.2 Wait Controller Related Registers

Shows the Wait Controller related register map, including CS Area Wait Control Registers.

CHAPTER 17 RAM BACKUP MODE

17.1 Outline of RAM Backup Mode

Describes RAM backup mode where internal RAM contents are retained when power is off, used for power saving or when power is down.

CHAPTER 19 JTAG

19.1 Outline of JTAG

19.3 JTAG Registers

19.4 Basic Operation of JTAG

CHAPTER 21 ELECTRICAL CHARACTERISTICS

21.1 Absolute Maximum Ratings

Lists the absolute maximum ratings for various parameters such as power supply, input/output voltage, and temperature.

21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz

21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz

21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz

21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz

21.7 A.C. Characteristics (when VCCE = 5 V)

21.8 A.C. Characteristics (when VCCE = 3.3 V)

APPENDIX 4 SUMMARY OF PRECAUTIONS

Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory

Details precautions for programming/erasing internal flash memory, including voltage transitions and pin usage.

Appendix 4.9 Precautions about the A-D Converters