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11-24
A-D Converters
32180 Group User's Manual (Rev.1.0)
11.2 A-D Converter Related Registers
11.2.5 A-D Conversion Speed Control Registers
A-D0 Conversion Speed Control Register (AD0CVSCR)
<Address: H
’0080 0087>A-D1 Conversion Speed Control Register (AD1CVSCR)
<Address: H
’0080 0A87>9 1011121314b15b8
ADCVSD
0
<After reset: H’00>
b Bit Name Function R W
8–14 No function assigned. Fix to "0". 00
15 ADCVSD (Note 1) 0: Slow mode R W
A-D conversion speed control bit 1: Fast mode
Note 1: The A-D conversion speed is determined by a combination of ADCVSD bit and A-D Single Mode Register 1’s relevant bit
during single mode, or a combination of ADCVSD bit and A-D Scan Mode Register 1’s relevant bit during scan mode.
The A-D Conversion Speed Control Registers control the A-D conversion speed during single and scan modes
of the A-D Converter.
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