18
18-7
OSCILLATOR CIRCUIT
32180 Group User's Manual (Rev.1.0)
18.1.4 System Clock Output Function
A clock whose frequency is twice that of the input clock (i.e., the peripheral clock) can be output from the BCLK
pin. The BCLK pin is shared with port P70. To use this pin to output the peripheral clock, set the P7 Operation
Mode Register (P7MOD) bit 8 to "1".
Configuration of the P7 Operation Mode Register is shown below.
P7 Operation Mode Register (P7MOD)
<Address: H
’0080 0747><After reset: H’00>
b Bit Name Function R W
8 P70MD 0:P70 R W
Port P70 operation mode bit 1:BCLK
9 P71MD 0:P71 R W
Port P71 operation mode bit 1:WAIT#
10 P72MD 0:P72 R W
Port P72 operation mode bit 1:HREQ#
11 P73MD 0:P73 R W
Port P73 operation mode bit 1:HACK#
12 P74MD 0:P74 R W
Port P74 operation mode bit 1:RTDTXD
13 P75MD 0:P75 R W
Port P75 operation mode bit 1:RTDRXD
14 P76MD 0:P76 R W
Port P76 operation mode bit 1:RTDACK
15 P77MD 0:P77 R W
Port P77 operation mode bit 1:RTDCLK
18.1.5 Oscillation Stabilization Time at Power-On
The oscillator circuit comprised of a ceramic (or crystal) resonator requires a finite time before its oscillation
stabilizes after being powered on. Therefore, there must be a certain amount of oscillation stabilization time that
suits the oscillator circuit used.
Figure 18.1.5 shows an oscillation stabilization time required at power-on.
18.1 Oscillator Circuit
9 1011121314b15b8
P70MD P71MD
P72MD P73MD P74MD P75MD P76MD P77MD
00000000
Figure 18.1.5 Oscillation Stabilization Time at Power-On
RESET#
XIN
Oscillation stabilization time
OSC-VCC
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