Renesas M32R/ECU Series

10
10-35
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
32180 Group User’s Manual (Rev.1.0)
10.2.6 Interrupt Control Unit
The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer.
Following timer interrupt control registers are provided for each timer:
• TOP0–5 Interrupt Request Status Register (TOP05IST)
• TOP0–5 Interrupt Request Mask Register (TOP05IMA)
• TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS)
• TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS)
• TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS)
• TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS)
• TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS)
• TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS)
• TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS)
• TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS)
• TIN7–11 Interrupt Request Status Register (TIN711IST)
• TIN7–11 Interrupt Request Mask Register (TIN711IMA)
• TIN12–19 Interrupt Request Status Register (TIN1219IST)
• TIN12–19 Interrupt Request Mask Register (TIN1219IMA)
• TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS)
• TIN24,25 Interrupt Request Mask Register (TIN2425IMA)
• TIN24,25 Interrupt Request Status Register (TIN2425IST)
• TIN26,27 Interrupt Request Mask Register (TIN2627IMA)
• TIN26,27 Interrupt Request Status Register (TIN2627IST)
• TIN28,29 Interrupt Request Mask Register (TIN2829IMA)
• TIN28,29 Interrupt Request Status Register (TIN2829IST)
• TIN30–33 Interrupt Request Mask & Status Register (TIN3033IMS)
• TOU0 Interrupt Request Mask Register (TOU0IMA)
• TOU0 Interrupt Request Status Register (TOU0IST)
• TOU1 Interrupt Request Mask Register (TOU1IMA)
• TOU1 Interrupt Request Status Register (TOU1IST)
• TOU2 Interrupt Request Mask Register (TOU2IMA)
• TOU2 Interrupt Request Status Register (TOU2IST)
For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control
registers are included in the timer, and the interrupt request status flags are automatically managed within the
Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.”
• TOP10 TOP10 Output Interrupt Request (IRQ5)
• TID0 TID0 Output Interrupt Request (IRQ14)
• TID1 TID1 Output Interrupt Request (IRQ15)
• TID2 TID2 Output Interrupt Request (IRQ17)