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MULTIJUNCTION TIMERS
10.5 TMS (Input-Related 16-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
10.5.7 Operation of TMS Measure Input
(1) Outline of TMS measure input
In TMS measure input, when the timer is enabled (by writing to the enable bit in software), it starts counting
up synchronously with the count clock. Then when event input to TMS is detected while the timer is operat-
ing, the counter value is latched into measure registers 0–3. The timer stops counting at the same time count
is disabled by writing to the enable bit.
A TIN interrupt request can be generated by measure signal input from an external device. A TMS interrupt
request can be generated when the counter overflows.
Count clock
Counter
H'FFFF
H'0000
Enabled
(by writing to the
enable bit)
Measure
event 1
occurs
Undefined
Enable bit
Note: • This diagram does not show detailed timing information.
Measure 0 register
H'8000
Overflow
occurs
TIN15 interrupt request
H'C000
Measure 1 register
TIN14 interrupt request
Measure
event 0
occurs
TMS interrupt request
due to overflow
H'6000
H'D000
H'6000H'8000
Undefined
value
Undefined
H'D000
H'C000
Measure
event 1
occurs
Measure
event 0
occurs
Figure 10.5.3 Typical Operation of TMS Measure Input
(2) Precautions on using TMS measure input
The following describes precautions to be observed when using TMS measure input.
• If measure event input and write to the counter occur in the same clock period, the write value is set in the
counter while at the same time latched into the measure register.
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