8
8-8
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
32180 Group User’s Manual (Rev.1.0)
8.3.2 Port Direction Registers
P0 Direction Register (P0DIR)
<Address: H
’0080 0720>P1 Direction Register (P1DIR)
<Address: H
’0080 0721>P2 Direction Register (P2DIR)
<Address: H
’0080 0722>P3 Direction Register (P3DIR)
<Address: H
’0080 0723>P4 Direction Register (P4DIR)
<Address: H
’0080 0724>P6 Direction Register (P6DIR)
<Address: H
’0080 0726>P7 Direction Register (P7DIR)
<Address: H
’0080 0727>P8 Direction Register (P8DIR)
<Address: H
’0080 0728>P9 Direction Register (P9DIR)
<Address: H
’0080 0729>P10 Direction Register (P10DIR)
<Address: H
’0080 072A>P11 Direction Register (P11DIR)
<Address: H
’0080 072B>P12 Direction Register (P12DIR)
<Address: H
’0080 072C>P13 Direction Register (P13DIR)
<Address: H
’0080 072D>P14 Direction Register (P14DIR)
<Address: H
’0080 072E>P15 Direction Register (P15DIR)
<Address: H
’0080 072F>P16 Direction Register (P16DIR)
<Address: H
’0080 0730>P17 Direction Register (P17DIR)
<Address: H
’0080 0731>P18 Direction Register (P18DIR)
<Address: H
’0080 0732>P19 Direction Register (P19DIR)
<Address: H
’0080 0733>P20 Direction Register (P20DIR)
<Address: H
’0080 0734>P21 Direction Register (P21DIR)
<Address: H
’0080 0735>P22 Direction Register (P22DIR)
<Address: H
’0080 0736>9 10 11 12 13 14 b15)(b8
123456b7b0
Pn0DR Pn1DR Pn2DR Pn3DR Pn4DR Pn5DR Pn6DR Pn7DR
00000000
n = 0–22 (not including P5)
<After reset: H’00>
b Bit Name Function R W
0(b8) Pn0DR (Port Pn0 direction bit) 0: Input mode R W
1(b9) Pn1DR (Port Pn1 direction bit) 1: Output mode R W
2(b10) Pn2DR (Port Pn2 direction bit) RW
3(b11) Pn3DR (Port Pn3 direction bit) RW
4(b12) Pn4DR (Port Pn4 direction bit) RW
5(b13) Pn5DR (Port Pn5 direction bit) RW
6(b14) Pn6DR (Port Pn6 direction bit) RW
7(b15) Pn7DR (Port Pn7 direction bit) RW
Notes: • No direction bits are provided for the following ports (read as 0, writing has no effect):
P40, P60, P64, P80, P81, P90–P92, P120–P123, P170, P171, P204–P207, P221, P223
• After reset, all ports are set for input mode.
8.3 Input/Output Port Related Registers
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