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12-37
Serial I/O
12.4 Receive Operation in CSIO Mode
32180 Group User's Manual (Rev.1.0)
Figure 12.4.3 Example of CSIO Reception (When Received Normally)
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register
interrupt request bit cleared
<CSIO on receive side>
<CSIO on transmit side>
<CSIO on receive side>
SCLKO
TXD
SCLKI
RXD
Internal clock selected
External clock selected
Receive clock
(SCLKO)
Set
Receive enable bit
RXD
Receive status bit
Reception finished bit
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
(When receive error
interrupt is selected)
No interrupt request
Interrupt request accepted (Note 3)
Reception finished interrupt request
(Note 2)
Read from the
receive buffer
: Interrupt request generated : Processing by software
Automatically cleared for each
receive operation performed
Clock stops
Cleared
Set by a write to
the transmit buffer
b7 b6 b5 b4 b3 b2 b1 b0
12.4.6 Example of CSIO Receive Operation
The following shows a typical receive operation in CSIO mode.
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