Renesas M32R/ECU Series

5
5-7
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.2 ICU Related Registers
5.2.3 SBI (System Break Interrupt) Control Register
SBI (System Break Interrupt) Control Register (SBICR) <Address: H’0080 0006>
123456b7b0
SBIREQ
0
0
0
0
0
0
0
0
<After reset: H’00>
b Bit Name Function R W
0–6 No function assigned. Fix to "0" 00
7 SBIREQ 0: SBI not requested R(Note 1)
SBI request bit 1: SBI requested
Note 1: This bit can only be cleared (see below)
The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin.
When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt
(SBI) request is generated to the CPU.
This bit cannot be set to "1" in software, it can only be cleared.
To clear this bit to "0", follow the procedure described below.
1. Write "1" to the SBI request bit.
2. Write "0" to the SBI request bit.
Note: • Unless this bit is set to "1", do not perform the above clearing operation.