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DMAC
32180 Group User’s Manual (Rev.1.0)
9.2 DMAC Related Registers
9.2.2 DMA Software Request Generation Registers
DMA0 Software Request Generation Register (DM0SRI)
<Address: H
’0080 0460>DMA1 Software Request Generation Register (DM1SRI)
<Address: H
’0080 0462>DMA2 Software Request Generation Register (DM2SRI)
<Address: H
’0080 0464>DMA3 Software Request Generation Register (DM3SRI)
<Address: H
’0080 0466>DMA4 Software Request Generation Register (DM4SRI)
<Address: H
’0080 0468>DMA5 Software Request Generation Register (DM5SRI)
<Address: H
’0080 0470>DMA6 Software Request Generation Register (DM6SRI)
<Address: H
’0080 0472>DMA7 Software Request Generation Register (DM7SRI)
<Address: H
’0080 0474>DMA8 Software Request Generation Register (DM8SRI)
<Address: H
’0080 0476>DMA9 Software Request Generation Register (DM9SRI)
<Address: H
’0080 0478>b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15
DM0SRI–DM9SRI
????????????????
<After reset: Undefined>
b Bit Name Function R W
0–15 DM0SRI–DM9SRI DMA transfer request is generated by writing any H W
DMA software request generation bits data to these bits.
Note: • This register may be accessed in either bytes or halfwords.
The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA
transfer request can be generated by writing any data to this register when “Software start” has been selected
for the cause of DMA transfer request.
(1) DM0SRI–DM9SRI (DMA Software Request Generation) bits
A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in
byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA
transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to ‘00’).
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