Renesas M32R/ECU Series - DMA Channel Control Registers

9
9-6
DMAC
32180 Group User’s Manual (Rev.1.0)
9.2.1 DMA Channel Control Registers
DMA0 Channel Control Register 0 (DM0CNT0) <Address: H’0080 0410>
123456b7b0
SADSL0 DADSL0
MDSEL0 TREQF0
REQSL0
TENL0 TSZSL0
000000 00
<After reset: H’00>
b Bit Name Function R W
0 MDSEL0 0: Normal mode R W
DMA0 transfer mode select bit 1: Ring buffer mode
1 TREQF0 0: Transfer not requested R(Note 1)
DMA0 transfer request flag bit 1: Transfer requested
2, 3 REQSL0 00: Software start or one DMA2 transfer completed R W
DMA0 transfer request source select bit 01: A-D0 conversion completed
10: MJT (TIO8_udf)
11: Extended DMA0 transfer request source select
(DMA0 Channel Control Register 1)
4 TENL0 0: Disable transfer R W
DMA0 transfer enable bit 1: Enable transfer
5 TSZSL0 0: 16 bits R W
DMA0 transfer size select bit 1: 8 bits
6 SADSL0 0: Fixed R W
DMA0 source address direction select bit 1: Increment
7 DADSL0 0: Fixed R W
DMA0 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA0 Channel Control Register 1 (DM0CNT1) <Address: H’0080 0411>
9 1011121314b15b8
REQESEL0
0000
0
0
0
0
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL0 0000: MJT (input event bus 2) R W
Extended DMA0 transfer request source select bit 0001: MJT (TID0_udf/ovf)
0010: CAN (CAN0_S0/S15)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
9.2 DMAC Related Registers
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