Renesas M32R/ECU Series - Page 212

9
DMAC
9-7
32180 Group User’s Manual (Rev.1.0)
9.2 DMAC Related Registers
DMA1 Channel Control Register 0 (DM1CNT0) <Address: H’0080 0420>
123456b7b0
SADSL1 DADSL1
MDSEL1 TREQF1
REQSL1
TENL1 TSZSL1
000000 00
<After reset: H’00>
b Bit Name Function R W
0 MDSEL1 0: Normal mode R W
DMA1 transfer mode select bit 1: Ring buffer mode
1 TREQF1 0: Transfer not requested R(Note 1)
DMA1 transfer request flag bit 1: Transfer requested
2, 3 REQSL1 00: Software start R W
DMA1 transfer request source select bit 01: MJT (output event bus 0)
10: MJT (TIN13S)
11: Extended DMA1 transfer request source select
(DMA1 Channel Control Register 1)
4 TENL1 0: Disable transfer R W
DMA1 transfer enable bit 1: Enable transfer
5 TSZSL1 0: 16 bits R W
DMA1 transfer size select bit 1: 8 bits
6 SADSL1 0: Fixed R W
DMA1 source address direction select bit 1: Increment
7 DADSL1 0: Fixed R W
DMA1 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA1 Channel Control Register 1 (DM1CNT1) <Address: H’0080 0421>
9 1011121314b15b8
REQESEL1
0000
0
0
0
0
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL1 0000: One DMA0 transfer completed R W
Extended DMA1 transfer request source select bit 0001: MJT(TIN3S)
0010: MJT(TID1_udf/ovf)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
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