9
9-8
DMAC
32180 Group User’s Manual (Rev.1.0)
DMA2 Channel Control Register 0 (DM2CNT0)
<Address: H
’0080 0430>123456b7b0
SADSL2 DADSL2MDSEL2 TREQF2
REQSL2
TENL2 TSZSL2
00000000
<After reset: H’00>
b Bit Name Function R W
0 MDSEL2 0: Normal mode R W
DMA2 transfer mode select bit 1: Ring buffer mode
1 TREQF2 0: Transfer not requested R(Note 1)
DMA2 transfer request flag bit 1: Transfer requested
2, 3 REQSL2 00: Software start R W
DMA2 transfer request source select bit 01: MJT (output event bus 1)
10: MJT (TIN18S)
11: Extended DMA2 transfer request source select
(DMA2 Channel Control Register 1)
4 TENL2 0: Disable transfer R W
DMA2 transfer enable bit 1: Enable transfer
5 TSZSL2 0: 16 bits R W
DMA2 transfer size select bit 1: 8 bits
6 SADSL2 0: Fixed R W
DMA2 source address direction select bit 1: Increment
7 DADSL2 0: Fixed R W
DMA2 destination address direction select bit 1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA2 Channel Control Register 1 (DM2CNT1)
<Address: H
’0080 0431>9 10 11 12 13 14 b15b8
REQESEL2
0000
<After reset: H’00>
b Bit Name Function R W
8–11 No function assigned. Fix to "0". 00
12–15 REQESEL2 0000: One DMA1 transfer completed R W
Extended DMA1 transfer request source select bit 0001: MJT(TID2_udf/ovf)
0010: CAN(CAN0_S1/S14)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
1111: Settings inhibited
9.2 DMAC Related Registers
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