Renesas M32R/ECU Series User Manual

5
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INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.3 Interrupt Request Sources in Internal Peripheral I/O
The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O,
A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal
peripheral I/O is described.
Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O
Interrupt Request Sources Contents Number of ICU Type of Input
Input Sources Source ( Note 1)
TIN3–6 input interrupt request TIN3–TIN6 inputs 4 Level-recognized
TIN20–29 input interrupt request TIN20–TIN29 inputs 10 Level-recognized
TIN12–19 input interrupt request TIN12–TIN19 inputs 8 Level-recognized
TIN0–2 input interrupt request TIN0–TIN2 inputs 3 Level-recognized
TIN7–11 input interrupt request TIN7–TIN11 inputs 5 Level-recognized
TMS0,1 output interrupt request TMS0, TMS1 output 2 Level-recognized
TOP8,9 output interrupt request TOP8, TOP9 output 2 Level-recognized
TOP10 output interrupt request TOP10 output 1 Edge-recognized
TIO4–7 output interrupt request TIO4–TIO7 outputs 4 Level-recognized
TIO8,9 output interrupt request TIO8, TIO9 outputs 2 Level-recognized
TOP0–5 output interrupt request TOP0–TOP5 outputs 6 Level-recognized
TOP6,7 output interrupt request TOP6–TOP7 outputs 2 Level-recognized
TIO0–3 output interrupt request TIO0–TIO3 outputs 4 Level-recognized
DMA0-4 interrupt request DMA0–4 transfer completed 5 Level-recognized
SIO1 receive interrupt request SIO1 reception-completed or receive error interrupt 1 Edge-recognized
SIO1 transmit interrupt request SIO1 transmission-completed or transmit buffer empty 1 Edge-recognized
interrupt
SIO0 receive interrupt request SIO0 reception-completed or receive error interrupt 1 Edge-recognized
SIO0 transmit interrupt request SIO0 transmission-completed or transmit buffer empty 1 Edge-recognized
interrupt
A-D0 conversion interrupt request A-D0 converter’s scan mode one-shot operation, 1 Edge-recognized
single mode or comparate mode completed
TID0 output interrupt request TID0 output 1 Edge-recognized
TOU0 output interrupt request TOU0_0–TOU0_7 outputs 8 Level-recognized
DMA5–9 interrupt request DMA5–9 transfer completed 5 Level-recognized
SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, 4 Level-recognized
request transmission-completed or transmit buffer empty interrupt
RTD interrupt request RTD interrupt generation command 1 Edge-recognized
TID1 output interrupt request TID1 output 1 Edge-recognized
TOU1,2 output interrupt request TOU1_0–TOU1_7 outputs, TOU2_0–TOU2_7 outputs 16 Level-recognized
SIO4,5 transmit/receive interrupt SIO4,5 reception-completed or receive error interrupt, 4 Level-recognized
request transmission-completed or transmit buffer empty interrupt
A-D1 conversion interrupt request A-D1 converter’s scan mode one-shot operation, 1 Edge-recognized
single mode or comparate mode completed
TID2 output interrupt request TID2 output 1 Edge-recognized
TIN30–33 input interrupt request TIN30–TIN33 inputs 4 Level-recognized
CAN0 transmit/receive & error CAN0 transmission or reception completed, CAN0 error 35 Level-recognized
interrupt request passive, CAN0 error bus-off, CAN0 bus error, single shot
CAN1 transmit/receive & error CAN1 transmission or reception completed, CAN1 error 35 Level-recognized
interrupt request passive, CAN1 error bus-off, CAN1 bus error, single shot
Note 1: ICU type of input source
• Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.
• Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For
this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.
5.3 Interrupt Request Sources in Internal Peripheral I/O

Renesas M32R/ECU Series Specifications

General

Brand	Renesas
Model	M32R/ECU Series
Category	Computer Hardware
Language	English

Summary

Before Use

Guide to Understanding the Register Table

Explains the conventions used in register tables, including bit numbering, register borders, status after reset, shaded bits, and read/write conditions.

CHAPTER 1 OVERVIEW

1.1 Outline of the 32180 Group

Provides an overview of the 32180 group, belonging to the M32R/ECU series of Mitsubishi microcomputers.

1.3 Pin Functions

Describes the functions of each pin on the 32180, including primary and alternative functions.

1.4 Pin Assignments

Provides the pin assignment diagram and table for the 240QFP package.

CHAPTER 4 EIT

4.2 EIT Events

Details the types of exceptions (RIE, AE, FPE), underflow, inexact, and zero division exceptions.

CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5.2 ICU Related Registers

Shows a register map associated with the Interrupt Controller (ICU), including Interrupt Vector Register and Interrupt Request Mask Register.

CHAPTER 6 INTERNAL MEMORY

6.1 Outline of the Internal Memory

Details the types of memory contained within the 32180: 48-Kbyte RAM and 1-Mbyte flash memory.

6.5 Programming the Internal Flash Memory

Explains the methods for programming or erasing the internal flash memory, including boot mode and single-chip mode.

CHAPTER 7 RESET

7.1 Outline of Reset

Describes the microcomputer reset mechanism via the RESET# input pin and the execution from the reset vector entry.

7.2 Reset Operation

Details reset operations such as power-on reset, reset during operation, reset at entering RAM backup mode, and reset vector relocation during flash programming.

CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.1 Outline of Input/Output Ports

Details the total number of input/output ports and their dual/triple function capabilities.

8.2 Selecting Pin Functions

Explains how pin functions are selected based on the current operation mode or by setting port operation mode registers.

8.3 Input/Output Port Related Registers

Lists the port data registers, port direction registers, and port operation mode registers.

CHAPTER 9 DMAC

9.2 DMAC Related Registers

Shows a memory map of the DMAC related registers, including channel control, source address, and destination address registers.

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers

Introduces the multijunction timers (MJT), their input/output event buses, and the six types of MJT provided.

10.2 Common Units of Multijunction Timers

Details the common units within MJTs: Prescaler, Clock Bus, Input/Output Event Bus Control, Input Processing, Output Flip-flop, and Interrupt Control Units.

10.3 TOP (Output-Related 16-Bit Timer)

Describes the TOP timer, its specifications, modes of operation (single-shot, delayed, continuous), and interrupt generation.

CHAPTER 11 A-D CONVERTERS

11.2 A-D Converter Related Registers

Shows the A-D converter related register map, including single mode, scan mode, and data registers.

11.3 Functional Description of A-D Converters

Explains how to find analog input voltages, A-D conversion by successive approximation, comparator operation, and conversion time.

CHAPTER 12 SERIAL I/O

12.2 Serial I/O Related Registers

Shows the serial I/O related register map, including interrupt and buffer registers.

CHAPTER 13 CAN MODULE

13.2 CAN Module Related Registers

Provides the CAN module related register map, covering control, status, frame format, and mask registers.

CHAPTER 14 REAL TIME DEBUGGER (RTD)

14.1 Outline of the Real-Time Debugger (RTD)

Explains the RTD as a serial I/O for reading/writing internal RAM locations via external commands without stopping the CPU.

14.3 Functional Description of the RTD

Details RTD operations for commands like VER, VEI, RDR, WRR, and RCV.

CHAPTER 15 EXTERNAL BUS INTERFACE

15.2 External Bus Interface Related Registers

Shows the register map for the external bus interface, including port operation mode registers.

CHAPTER 16 WAIT CONTROLLER

16.2 Wait Controller Related Registers

Shows the Wait Controller related register map, including CS Area Wait Control Registers.

CHAPTER 17 RAM BACKUP MODE

17.1 Outline of RAM Backup Mode

Describes RAM backup mode where internal RAM contents are retained when power is off, used for power saving or when power is down.

CHAPTER 19 JTAG

19.1 Outline of JTAG

19.3 JTAG Registers

19.4 Basic Operation of JTAG

CHAPTER 21 ELECTRICAL CHARACTERISTICS

21.1 Absolute Maximum Ratings

Lists the absolute maximum ratings for various parameters such as power supply, input/output voltage, and temperature.

21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz

21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz

21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz

21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz

21.7 A.C. Characteristics (when VCCE = 5 V)

21.8 A.C. Characteristics (when VCCE = 3.3 V)

APPENDIX 4 SUMMARY OF PRECAUTIONS

Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory

Details precautions for programming/erasing internal flash memory, including voltage transitions and pin usage.

Appendix 4.9 Precautions about the A-D Converters