2
2-3
32180 Group User’s Manual (Rev.1.0)
CPU
2.3 Control Registers
2.3.1 Processor Status Word Register: PSW (CR0)
0000 000 0000000
7654321 8 9 10 11 12 13 14 b15b0
?? 00000?00000000
BC SM IE C
23 24 25 26 27 28 29 30 b3117 18 19 20 21 22b16
BIEBSM
BPSW field
0 0
PSW field
<After reset: B’0000 0000 0000 0000 ??00 000? 0000 0000>
b Bit Name Function R W
0–15 No function assigned. Fix to "0". 00
16 BSM Saves value of SM bit when EIT occurs R W
Backup SM Bit
17 BIE Saves value of IE bit when EIT occurs R W
Backup IE Bit
18–22 No function assigned. Fix to "0". 00
23 BC Saves value of C bit when EIT occurs R W
Backup C Bit
24 SM 0: Uses R15 as the interrupt stack pointer R W
Stack Mode Bit 1: Uses R15 as the user stack pointer
25 IE 0: Does not accept interrupt R W
Interrupt Enable Bit 1: Accepts interrupt
26–30 No function assigned. Fix to "0". 00
31 C Indicates carry, borrow or overflow resulting R W
Condition Bit from operations (instruction dependent)
The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field
which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs.
The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit.
The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the
Backup Condition (BC) bit.
After reset, BSM, BIE and BC are undefined. All other bits are "0".
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