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MULTIJUNCTION TIMERS
10.6 TML (Input-Related 32-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
10.6.2 Outline of TML Operation
In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is
a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at
that point in time is stored in each 32-bit measure register.
When the reset input signal is deasserted, the counter starts operating with a BCLK/2 clock, and cannot be
stopped once it has started. The counter is idle only when the microcomputer remains reset.
A TIN interrupt request can be generated by external measure signal input. However, no TML counter overflow
interrupts are available.
10.6.3 TML Related Register Map
Shown below is a TML related register map.
TML Related Register Map
Address +0 address +1 address See pages
b0 b7 b8 b15
H'0080 03E0 TML0 Counter (Upper) 10-135
(TML0CT)
H'0080 03E2 (Lower)
H'0080 03EA (Use inhibited area) TML0 Control Register 10-134
(TML0CR)
(Use inhibited area)
H'0080 03F0 TML0 Measure 3 Register (Upper) 10-135
(TML0MR3)
H'0080 03F2 (Lower)
H'0080 03F4 TML0 Measure 2 Register (Upper) 10-135
(TML0MR2)
H'0080 03F6 (Lower)
H'0080 03F8 TML0 Measure 1 Register (Upper) 10-135
(TML0MR1)
H'0080 03FA (Lower)
H'0080 03FC TML0 Measure 0 Register (Upper) 10-135
(TML0MR0)
H'0080 03FE (Lower)
H'0080 0FE0 TML1 Counter (Upper) 10-135
(TML1CT)
H'0080 0FE2 (Lower)
(Use inhibited area)
H'0080 0FEA (Use inhibited area) TML1 Control Register 10-134
(TML1CR)
(Use inhibited area)
H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-135
(TML1MR3)
H'0080 0FF2 (Lower)
H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-135
(TML1MR2)
H'0080 0FF6 (Lower)
H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-135
(TML1MR1)
H'0080 0FFA (Lower)
H'0080 0FFC TML1 Measure 0 Register (Upper) 10-135
(TML1MR0)
H'0080 0FFE (Lower)
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