5
5-10
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)
5.2 ICU Related Registers
Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type)
(2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15)
These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’
to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O.
When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt
sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether
to forward an EI request to the CPU or keep the interrupt request pending.
The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts
are accepted.
Table 5.2.1 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set IMASK values at which interrupts are accepted
0 (ILEVEL = "000") Accepted when IMASK is 1–7
1 (ILEVEL = "001") Accepted when IMASK is 2–7
2 (ILEVEL = "010") Accepted when IMASK is 3–7
3 (ILEVEL = "011") Accepted when IMASK is 4–7
4 (ILEVEL = "100") Accepted when IMASK is 5–7
5 (ILEVEL = "101") Accepted when IMASK is 6–7
6 (ILEVEL = "110") Accepted when IMASK is 7
7 (ILEVEL = "111") Not accepted (interrupts disabled)
Interrupt request from
each internal peripheral I/O
Interrupt enabled
ILEVEL
(levels 0-7)
Data bus
Bits 5-7 or bits 13-15
3
F/F
Set
Set/clear
IREQ
Interrupt priority
resolving circuit
F/F
Reset
IVECT read
IMASK write
Clear
To the CPU core
Bit 3 or 11
Set EI
Interrupt request from each
group internal peripheral I/O
Interrupt enabled
b3, b11
Data bus
b5-b7, b13-b15
Read
3
IREQ
Read-only circuit
ILEVEL
(levels 0-7)
Group interrupt
Interrupt priority
resolving circuit
F/F
Clear
To the CPU core
Set
EI
Reset
IVECT read
IMASK write
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