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MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
32180 Group User’s Manual (Rev.1.0)
To the Interrupt
Controller
Timer or TIN input
interrupt request
Interrupt request status
Data bus
Set
Group interrupt
Interrupt request enabled
clear
F/F
F/F
Data = 0
Figure 10.2.3 Interrupt Request Status and Mask Registers
For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers
are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in
the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and
cannot be accessed for write.
(1) Interrupt request status bit
This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs,
this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has
no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt
request mask bit, it can be used to inspect the operating status of peripheral functions.
In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the
interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been
serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit.
(2) Interrupt request mask bit
This bit is used to disable unnecessary interrupts within the grouped interrupt request. Set this bit to "0" to
enable interrupt requests or "1" to disable interrupt requests.
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