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A-D Converters
32180 Group User's Manual (Rev.1.0)
11.2 A-D Converter Related Registers
(1) ADCSPD (A-D Conversion Speed Select) bit (Bit 9)
This bit selects an A-D conversion speed when the A-D Converter is operating in scan mode. Setting this bit
to selects normal speed, and setting this bit to "1" selects double speed.
(2) ADCSHSL (A-D Conversion Method Select) bit (Bit 10)
This bit enables or disables the sample-and-hold function when the A-D Converter is operating in scan mode.
Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample-
and-hold function.
(3) ADSSHSPD (A-D Sample-and-Hold Speed Select) bit (Bit 11)
When the A-D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When
this bit is "0", the conversion speed is the same as normal A-D conversion speed. When this bit is "1",
conversion is performed at a speed faster than normal A-D conversion speed.
Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADCSHSL (A-D
conversion method select) bit to "0".
For details about the conversion time, see Section 11.3.4, “Calculating the A-D Conversion Time.”
(4) ANSCAN (A-D Scan Loop Select) bits (Bits 12–15)
The ANSCAN (A-D scan loop select) bits set the channels to be scanned during scan mode of the A-D
Converter.
The ANSCAN (A-D scan loop select) bits when accessed for read during scan operation serve as a status
register indicating the channel being scanned.
The value read from these bits during single mode is always B’0000.
If A-D conversion is stopped by setting A-D Scan Mode Register 0 ADCSTP (A-D conversion stop) bit to "1"
while executing scan mode, the value read from these bits indicates the channel whose A-D conversion has
been canceled.
Also, if read during single mode conversion of special operation mode “Forcible single mode execution dur-
ing scan mode,” the value of these bits indicates the channel whose A-D conversion has been canceled in
the middle of scan.
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