7
7-2
RESET
32180 Group User’s Manual (Rev.1.0)
7.1 Outline of Reset
The microcomputer is reset by applying a low-level signal to the RESET# input pin. The microcomputer is gotten
out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in
the Program Counter (PC) and the CPU starts executing from the reset vector entry.
7.2 Reset Operation
When a low-level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the
RESET# pin, the microcomputer is reset. At this time, pins on the microcomputer are reset (see the Pin State
When Reset in Table 1.4.1, “Pin Assignments”), and an internal bus hold request signal is output internally. Fur-
thermore, the internal circuits (including the CPU) are reset 9–10 BCLK periods later.
When the RESET# input is returned high, the microcomputer pins get out of a reset state and the internal bus hold
request is deasserted 17–18 BCLK periods later. Then the internal circuits get out of a reset state 15 BCLK
periods after that.
7.1 Outline of Reset
Noise Canceller
S
R
OVF
Pin reset signal
Internal circuit reset signal
Flip-flop
Counter
RESET#
Extended for a duration during which
the RESET# input is held low
17–18BCLK
15BCLK
9–10BCLK
RESET# pin
Reset signal (internal signal)
past the noise canceller
Pin reset (Note 2) and
internal bus hold request
(internal signal)
Internal circuit reset
(internal signal)
Duration needed for
noise cancellation (Note 1)
200ns
Note 1: If the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller.
Note 2: The port-related registers also are reset.
Figure 7.2.2 Reset Sequence
Figure 7.2.1 Reset Circuit
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