Renesas M32R/ECU Series User Manual

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OVERVIEW
32180 Group User’s Manual (Rev.1.0)
1.2 Block Diagram
Table 1.2.1 Features of the 32180 (1/2)
Functional Block Features
M32R-FPU CPU core • Implementation: Five-stage pipelined instruction processing (processed in six stages when
performing floating-point arithmetic)
• Internal 32-bit structure of the core
• Register configuration
General-purpose registers: 32 bits × 16 registers
Control registers: 32 bits × 6 registers
• Instruction set
16 and 32-bit instruction formats
100 discrete instructions and six addressing modes
• Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)
• Internal single-precision floating-point arithmetic unit (FPU)
RAM • Capacity: 48 Kbytes, accessible with zero wait state
• The internal RAM can be accessed for reading or rewriting data from the outside independently of
the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to
decrease.
Flash memory • Capacity: 1 Mbytes (1,024 Kbytes), accessible with one wait state
• Durability: Rewritable 100 times
Bus specification • Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz)
• Logical address space : 4 Gbytes linear
• Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)
(or accessed in 64 bits when accessing the internal flash memory for
instructions)
: Internal 16-bit data bus (for internal peripheral I/O access)
• External area: Maximum 8 Mbytes (during processor mode)
• Extended external area: Maximum 8 Mbytes (1 Mbytes + 2 Mbytes × 3 blocks during external
extension mode)
• External data address: 20-bit address
• External data bus: 16-bit data bus
• Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write
Multijunction timer (MJT) • 64-channel multi-functional timer
16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,
16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels,
16-bit input related up/down timer × 3 channels, and 24-bit output related timer × 24 channels
• Flexible timer configuration is possible by interconnecting these timer channels.
• Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level
from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)
• DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or
low level from the TIN pin (These can be used as external DMA transfer request inputs
irrespective of timer operation.)
DMAC • Number of channels: 10
• Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O
and internal RAM are supported.
• Capable of advanced DMA transfers when used in combination with internal peripheral I/O
• Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)
• DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a
transfer on another channel.)
• Interrupt request: DMA transfer counter register underflow

Renesas M32R/ECU Series Specifications

General

Brand	Renesas
Model	M32R/ECU Series
Category	Computer Hardware
Language	English

Summary

Before Use

Guide to Understanding the Register Table

Explains the conventions used in register tables, including bit numbering, register borders, status after reset, shaded bits, and read/write conditions.

CHAPTER 1 OVERVIEW

1.1 Outline of the 32180 Group

Provides an overview of the 32180 group, belonging to the M32R/ECU series of Mitsubishi microcomputers.

1.3 Pin Functions

Describes the functions of each pin on the 32180, including primary and alternative functions.

1.4 Pin Assignments

Provides the pin assignment diagram and table for the 240QFP package.

CHAPTER 4 EIT

4.2 EIT Events

Details the types of exceptions (RIE, AE, FPE), underflow, inexact, and zero division exceptions.

CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5.2 ICU Related Registers

Shows a register map associated with the Interrupt Controller (ICU), including Interrupt Vector Register and Interrupt Request Mask Register.

CHAPTER 6 INTERNAL MEMORY

6.1 Outline of the Internal Memory

Details the types of memory contained within the 32180: 48-Kbyte RAM and 1-Mbyte flash memory.

6.5 Programming the Internal Flash Memory

Explains the methods for programming or erasing the internal flash memory, including boot mode and single-chip mode.

CHAPTER 7 RESET

7.1 Outline of Reset

Describes the microcomputer reset mechanism via the RESET# input pin and the execution from the reset vector entry.

7.2 Reset Operation

Details reset operations such as power-on reset, reset during operation, reset at entering RAM backup mode, and reset vector relocation during flash programming.

CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.1 Outline of Input/Output Ports

Details the total number of input/output ports and their dual/triple function capabilities.

8.2 Selecting Pin Functions

Explains how pin functions are selected based on the current operation mode or by setting port operation mode registers.

8.3 Input/Output Port Related Registers

Lists the port data registers, port direction registers, and port operation mode registers.

CHAPTER 9 DMAC

9.2 DMAC Related Registers

Shows a memory map of the DMAC related registers, including channel control, source address, and destination address registers.

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers

Introduces the multijunction timers (MJT), their input/output event buses, and the six types of MJT provided.

10.2 Common Units of Multijunction Timers

Details the common units within MJTs: Prescaler, Clock Bus, Input/Output Event Bus Control, Input Processing, Output Flip-flop, and Interrupt Control Units.

10.3 TOP (Output-Related 16-Bit Timer)

Describes the TOP timer, its specifications, modes of operation (single-shot, delayed, continuous), and interrupt generation.

CHAPTER 11 A-D CONVERTERS

11.2 A-D Converter Related Registers

Shows the A-D converter related register map, including single mode, scan mode, and data registers.

11.3 Functional Description of A-D Converters

Explains how to find analog input voltages, A-D conversion by successive approximation, comparator operation, and conversion time.

CHAPTER 12 SERIAL I/O

12.2 Serial I/O Related Registers

Shows the serial I/O related register map, including interrupt and buffer registers.

CHAPTER 13 CAN MODULE

13.2 CAN Module Related Registers

Provides the CAN module related register map, covering control, status, frame format, and mask registers.

CHAPTER 14 REAL TIME DEBUGGER (RTD)

14.1 Outline of the Real-Time Debugger (RTD)

Explains the RTD as a serial I/O for reading/writing internal RAM locations via external commands without stopping the CPU.

14.3 Functional Description of the RTD

Details RTD operations for commands like VER, VEI, RDR, WRR, and RCV.

CHAPTER 15 EXTERNAL BUS INTERFACE

15.2 External Bus Interface Related Registers

Shows the register map for the external bus interface, including port operation mode registers.

CHAPTER 16 WAIT CONTROLLER

16.2 Wait Controller Related Registers

Shows the Wait Controller related register map, including CS Area Wait Control Registers.

CHAPTER 17 RAM BACKUP MODE

17.1 Outline of RAM Backup Mode

Describes RAM backup mode where internal RAM contents are retained when power is off, used for power saving or when power is down.

CHAPTER 19 JTAG

19.1 Outline of JTAG

19.3 JTAG Registers

19.4 Basic Operation of JTAG

CHAPTER 21 ELECTRICAL CHARACTERISTICS

21.1 Absolute Maximum Ratings

Lists the absolute maximum ratings for various parameters such as power supply, input/output voltage, and temperature.

21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz

21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz

21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz

21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz

21.7 A.C. Characteristics (when VCCE = 5 V)

21.8 A.C. Characteristics (when VCCE = 3.3 V)

APPENDIX 4 SUMMARY OF PRECAUTIONS

Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory

Details precautions for programming/erasing internal flash memory, including voltage transitions and pin usage.

Appendix 4.9 Precautions about the A-D Converters