10
10-81
MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined,
and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter,
letting it start counting. Thereafter, it continues counting down until it underflows after reaching the minimum
count.
Count clock
Correction register
H'FFFF
H'0000
Enabled
(by writing to the enable bit
or by external input)
F/F output
Disabled
(by underflow)
(Unused)
TOP interrupt request
due to underflow
Enable bit
Starts counting down from
the reload register set value
Note: • This diagram does not show detailed timing information.
Reload register
H'A000
Data inverted
by enable
Counter
H'A000
Data inverted
by underflow
H'FFFF
H'(A000-1)
Indeterminate
value
Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode
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