10
10-83
MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected
Data inverted
by enable
Data inverted
by underflow
H'(8000-1)
H'FFFF
H'0000
H'8000
H'5000
H'5000+H'4000
H'8000
H'FFFF
Undefined
H'4000
Count clock
Correction register
Enabled
(by writing to the enable bit
or by external input)
F/F output
TOP interrupt request
due to underflow
Enable bit
Note: • This diagram does not show detailed timing information.
Reload register
Write to the
correction register
Undefined
value
Disabled
(by underflow)
Counter
In the example below, the reload register is initially set to H’8000. When the timer starts, the reload register
value is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is
written to the correction register when the counter has counted down to H’5000. As a result of this correction,
the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 + H’4000 + 1)
before it stops.
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