10
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MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively.
When the timer is enabled, the counter starts counting down and when it underflows after reaching the
minimum count, the counter is loaded with the content of the reload register and continues counting down.
H'FFFF
H'0000
H'E000
H'A000
H'E000
H'(E000-1) H'(E000-1)
H'FFFF H'FFFF
Data inverted
by underflow
Data inverted
by underflow
Data inverted by
enable
Count clock
Correction register
F/F output
TOP interrupt request
due to underflow
Enable bit
Note: • This diagram does not show detailed timing information.
Reload register
Counter
Underflow
(first time)
Underflow
(second time)
Enabled
(by writing to the enable bit
or by external input)
Count down from the
counter's set value
Count down from the
reload register's
set value
Count down from the
reload register's
set value
(Unused)
Figure 10.3.18 Typical Operation in TOP Continuous Output Mode
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