Renesas M32R/ECU Series

10
10-139
MULTIJUNCTION TIMERS
10.7 TID (Input-Related 16-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
IRQ14
IRQ11
IRQ11
DMA0
TOU0_0–7en
TOU1_0–7en
TOU2_0–7en
TOU2_7udf
TOU1_7udf
TOU0_7udf
Output event bus 0
IRQ17
DMA2
IRQ15,
AD1TRG(To A-D1 converter)
DMA1
BCLK/2
TIN24(P172)
TIN25(P173)
IRQ11
IRQ11
BCLK/2
TIN26(P190)
TIN27(P191)
IRQ11
IRQ11
BCLK/2
TIN28(P192)
TIN29(P193)
TID 0
clk
CLK1 CLK2
ovf
udf
TIN25S
PRS3
TIN27S
TIN29S
S
S
S
TIN24S
TIN26S
TIN28S
Clock
control
Reload register
Up/down-counter
TID 1
clk
CLK1 CLK2
ovf
udf
Clock
control
Reload register
TID 2
clk
CLK1 CLK2
ovf
udf
Clock
control
Reload register
PRS4
PRS5
Up/down-counter
Up/down-counter
Figure 10.7.1 Block Diagram of TID (Input-Related 16-Bit Timer)
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating.
BCLK
Count clock
Enable
Count clock period
Count clock-dependent
delay
Write to the enable bit
Figure 10.7.2 Count Clock Dependent Delay