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10-163
MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
(2) TOU counters during PWM output and single-shot PWM output modes
TOU0_0 Counter (TOU00CT)
<Address: H
’0080 0792>TOU0_1 Counter (TOU01CT)
<Address: H
’0080 079A>TOU0_2 Counter (TOU02CT)
<Address: H
’0080 07A2>TOU0_3 Counter (TOU03CT)
<Address: H
’0080 07AA>TOU0_4 Counter (TOU04CT)
<Address: H
’0080 07B2>TOU0_5 Counter (TOU05CT)
<Address: H
’0080 07BA>TOU0_6 Counter (TOU06CT)
<Address: H
’0080 07C2>TOU0_7 Counter (TOU07CT)
<Address: H
’0080 07CA>TOU1_0 Counter (TOU10CT)
<Address: H
’0080 0B92>TOU1_1 Counter (TOU11CT)
<Address: H
’0080 0B9A>TOU1_2 Counter (TOU12CT)
<Address: H
’0080 0BA2>TOU1_3 Counter (TOU13CT)
<Address: H
’0080 0BAA>TOU1_4 Counter (TOU14CT)
<Address: H
’0080 0BB2>TOU1_5 Counter (TOU15CT)
<Address: H
’0080 0BBA>TOU1_6 Counter (TOU16CT)
<Address: H
’0080 0BC2>TOU1_7 Counter (TOU17CT)
<Address: H
’0080 0BCA>TOU2_0 Counter (TOU20CT)
<Address: H
’0080 0C92>TOU2_1 Counter (TOU21CT)
<Address: H
’0080 0C9A>TOU2_2 Counter (TOU22CT)
<Address: H
’0080 0CA2>TOU2_3 Counter (TOU23CT)
<Address: H
’0080 0CAA>TOU2_4 Counter (TOU24CT)
<Address: H
’0080 0CB2>TOU2_5 Counter (TOU25CT)
<Address: H
’0080 0CBA>TOU2_6 Counter (TOU26CT)
<Address: H
’0080 0CC2>TOU2_7 Counter (TOU27CT)
<Address: H
’0080 0CCA>b01234567891011121314b15
TOU00CT-TOU07CT, TOU10CT-TOU17CT, TOU20CT-TOU27CT
????????????????
<After reset: Undefined>
b Bit Name Function R W
0–15 TOU00CT–TOU07CT, 16-bit counter value R W
TOU10CT–TOU17CT,
TOU20CT–TOU27CT
Note: • This register must always be accessed in halfwords.
The TOU counters operate as a 16-bit down-counter when in PWM output or single-shot PWM output mode.
After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the
TOU enable source select bit), the counter starts counting synchronously with the count clock.
During single-shot output, delayed single-shot output and continuous output modes, the TOU counters operate
as a 24-bit down-counter, with the 8 high-order bits added. For details, see Section 10.8.5, Paragraph (1), “TOU
counters during single-shot output, delayed single-shot output and continuous output modes.”
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