11
11-19
A-D Converters
32180 Group User's Manual (Rev.1.0)
(1) ADSMSL (A-D Conversion Mode Select) bit (Bit 8)
This bit selects A-D conversion mode when the A-D Converter is operating in single mode. Setting this bit to
"0" selects A-D conversion mode, and setting this bit to "1" selects comparator mode.
(2) ADSSPD (A-D Conversion Speed Select) bit (Bit 9)
This bit selects the A-D conversion speed when the A-D Converter is operating in single mode. Setting this bit
to "0" selects normal speed, and setting this bit to "1" selects double speed.
(3) ADSSHSL (A-D Conversion Method Select) bit (Bit 10)
This bit enables or disables the sample-and-hold function when the A-D Converter is operating in single
mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the
sample-and-hold function.
Setting of this bit has no effect if comparator mode is selected with the ADSMSL (A-D conversion mode
select) bit.
(4) ADSSHSPD (A-D Sample-and-Hold Speed Select) bit (Bit 11)
When the A-D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When
this bit is "0", the conversion speed is the same as normal A-D conversion speed. When this bit is "1",
conversion is performed at a speed faster than normal A-D conversion speed.
Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADSSHSL (A-D
conversion method select) bit to "0".
For details about the conversion time, see Section 11.3.4, “Calculating the A-D Conversion Time.”
(5) ANSEL (A-D Analog Input Pin Select) bits (Bits 12–15)
These bits select the analog input pins when the A-D Converter is operating in single mode. A-D conversion
or comparate operation is performed on the channels selected with these bits. If these bits are accessed for
read, the value written to them is read out.
11.2 A-D Converter Related Registers
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