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12-16
Serial I/O
12.2 Serial I/O Related Registers
32180 Group User's Manual (Rev.1.0)
(4) PSEL (Odd/Even Parity Select) bit (Bit 13)
This bit is effective during UART mode. When parity is enabled (bit 14 = "1"), use this bit to select the parity
attribute (whether odd or even). Setting this bit to "0" selects an odd parity, and setting this bit to "1" selects
an even parity.
When parity is disabled (bit 14 = "0") and during clock-synchronous mode, the content of this bit has no effect.
(5) PEN (Parity Enable) bit (Bit 14)
This bit is effective during UART mode. When this bit is set to "1", a parity bit is added immediately after the
data bits of the transmit data, and the received data is checked for parity.
The parity bit added to the transmit data is automatically determined to be "0" or "1" so that the attribute (odd/
even) derived by adding the number of 1’s in data bits and the content of the parity bit agrees with one that
was selected with the odd/even parity select bit (bit 13).
Figure 12.2.7 shows an example of a data format when parity is enabled.
(6) SEN (Sleep Select) bit (Bit 15)
This bit is effective during UART mode. If the sleep function is enabled by setting this bit to "1", data is latched
into the UART Receive Buffer Register only when the most significant bit (MSB) of the received data is "1".
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