12
12-47
Serial I/O
12.6 Transmit Operation in UART Mode
32180 Group User's Manual (Rev.1.0)
Figure 12.6.6 Example of UART Transmission (Transmitted Successively)
: Processing by software
: Interrupt request generated
Set
Transmit buffer
empty bit
Transmit enable bit
Cleared
Transmit status bit
Transferred from the
transmit buffer to the
transmit shift register
(transmission starts)
TXD
SIO transmit interrupt request
(Note 1)
(First data) (Next data)
Write to the
transmit buffer
register
First data
Next data is written
upon transmit interrupt
(Note 5)
(Note 2)
(Note 2)
<UART on transmit side>
<UART on transmit side> <UART on receive side>
TXD
RXD
ST
b7
b0 STSP
b7
b0
SP
Cleared when transfer of
the last data is completed
Interrupt request accepted (Note 4)
Next data
(Note 2)(Note 6)
(Note 3)
(Note 3)(Note 7)
Interrupt request accepted (Note 4)
(When transmit buffer empty
interrupt is selected)
(When transmission finished
interrupt is selected)
Write to the
transmit buffer
register
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.
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