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12-53
SERIAL I/O
12.7 Receive Operation in UART Mode
32180 Group User's Manual (Rev.1.0)
Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred)
<UART on receive side>
<UART on receive side> <UART on transmit side>
TXD
RXD
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled
Note 3: When receive error interrupt is enabled
Note 4: This is done by clearing the receive enable bit to "0".
Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt
request bit cleared
Receive enable bit
SIO Receive Control Register)
b7
ST SP
SP
Reception finished bit
RXD
Set
: Processing by software : Interrupt request generated
ST
b7
Receive buffer not read
during this interval
First data reception
completed
Next data reception
completed
(Note 5)
Overrun error bit
cleared (Note 4)
Overrun error bit
Set
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
Reception finished
interrupt request
Interrupt request accepted (Note 5)
Receive error interrupt request
(Note 3)
Interrupt request accepted (Note 5)
(When receive error
interrupt is selected)
(Note 2)
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