15
15-20
EXTERNAL BUS INTERFACE
32180 Group User’s Manual (Rev.1.0)
(3) When the Bus Mode Control Register = "1" using a combination of 8/16-bit data bus memories
The diagram below shows a typical connection of external extension memory, with an 8-bit data bus memory
located in the CS0 area, and a 16-bit data bus memory located in the CS1 area. (External extension memory
can only be used in external extension mode and processor mode.)
15.5 Typical Connection of External Extension Memory
Memory mapping
Internal flash memory
(1024KB)
External memory area
(1MB)
When CL = 50 pF, memory can be connected with only 2 ns of data delay.
Normally used as port. WAIT is used only when seven or more wait states are needed.
H'0000 0000
H'0040 0000
H'0020 0000
H'000F FFFF
H'0010 0000
External memory area
(2MB)
1M-CS0 area
2M-CS1 area
SRAM
8-bit memory
A18
A1
D7
D0
RD#
CS#
max1MB
A19
A0
D15
D0
BHE#
CS#
WR#(D0-D15)
RD#(D0-D15)
max2MB
M32180F8
A11
A30
D0
D15
RD#
CS0#
CS1#
CS2#
CS3#
BHE#
WR#
WAIT#
QS32X2245
D7
D8
A B
OE
BLE#
BLE#
A0
8-bit bus area
16-bit bus area
Note: • The QS32X2245 is a product made by the IDT Company.
A B
Number of bus wait states can be set to 0-7.
WR#
Figure 15.5.3 Typical Connection of External Extension Memory (when BUSMOD bit = "1" using a combina-
tion of 8/16-Bit Memories)
Note: • The address and data are connected in such a way that pin 0 is the MSB and pin 15 is the LSB.
When connecting external extension memory, connections of the MSB and LSB sides must be
reversed.
To Next Page
Loading...
Need help?
General
