16
16-25
WAIT CONTROLLER
16.3 Typical Operation of the Wait Controller
32180 Group User’s Manual (Rev.1.0)
Figure 16.3.20 Read/Write Timing (Internal 1 Wait State + Recovery and Idle Cycles Added)
Read
Read (4 cycles)
BCLK
A11–A30
CS0#–CS3#
WR#
DB0–DB15
WAIT#
RD#
"H"
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Notes: • Circles in the above diagram indicate the sampling timing.
• BCLK is not output.
• No idle cycles are added after the write cycle.
(Don't Care)
BHE#, BLE#
Internal
1 wait state
(Don't Care)
"H"
Recovery
cycle
Write
Write (3 cycles)
BCLK
A11–A30
CS0#–CS3#
WR#
DB0–DB15
WAIT#
RD#
"H"
(Don't Care)
BHE#, BLE#
Internal
1 wait state
(Don't Care)
"H"
Recovery
cycle
Idle
cycle
Bus Mode Control Register (Note 1)
BUSMOD bit = 1 (byte enable separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 001 (1 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 1 (with recovery cycle)
IDLE bit = 1 (with idle cycle)
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