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21-23
ELECTRICAL CHARACTERISTICS
32180 Group User's Manual (Rev.1.0)
Symbol Parameter Rated Value Unit See Fig.
MIN MAX 21.7.14
tc(RTDCLK) RTDCLK Input Cycle Time 500 ns [82]
tw(RTDCLKH) RTDCLK Input High Pulse Width 230 ns [83]
tw(RTDCLKL) RTDCLK Input Low Pulse Width 230 ns [84]
td(RTDCLKH-RTDACK) RTDACK Delay Time after RTDCLK Input 160 ns [85]
tv(RTDCLKL-RTDACK) RTDACK Valid Time after RTDCLK Input 160 ns [86]
td(RTDCLKH-RTDTXD) RTDTXD Delay Time after RTDCLK Input 160 ns [87]
th(RTDCLKH-RTDRXD) RTDRXD Input Hold Time 50 ns [88]
tsu(RTDRXD-RTDCLKL) RTDRXD Input Setup Time 60 +160 ns [89]
(8) JTAG interface timing
Symbol Parameter Rated Value Unit See Fig.
MIN MAX 21.7.13
tc(JTCK) JTCK Input Cycle Time 100 ns [60]
tw(JTCKH) JTCK Input High Pulse Width 40 ns [61]
tw(JTCKL) JTCK Input Low Pulse Width 40 ns [62]
tsu(JTDI-JTCK) JTDI, JTMS Input Setup Time 15 ns [63]
th(JTCK-JTDI) JTDI, JTMS Input Hold Time 20 ns [64]
td(JTCK-JTDOV) JTDO Output Delay Time after JTCK Fall 40 ns [65]
td(JTCK-JTDOX) JTDO Output Hi-Z Delay Time after JTCK Fall 40 ns [66]
tw(JTRST) JTRST Input Low Pulse Width tc(JTCK) ns [67]
Note: • The rated values here are guaranteed for the case where the measured pin load capacitance CL = 80 pF.
(9) RTD timing
tc(RTDCLK)
2
21.7 A.C. Characteristics (when VCCE = 5 V)
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